SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
Hewlett-Packard Company
HP Integrity Superdome 16-way (1500 MHz Itanium 2)
SPECint_rate2000 = 229    
SPECint_rate_base2000 = 229    
SPEC license # 3 Tested by: HP Richardson Test date: Sep-2003 Hardware Avail: Oct-2003 Software Avail: Sep-2003
Graph Scale Benchmark Base
Copies
Base
Runtime
Base
Ratio
Copies Runtime Ratio
164.gzip base result bar (175)
164.gzip peak result bar (175)
164.gzip 16 148    175     16 148    175    
175.vpr base result bar (197)
175.vpr peak result bar (197)
175.vpr 16 132    197     16 132    197    
176.gcc base result bar (264)
176.gcc peak result bar (264)
176.gcc 16 77.2  264     16 77.2  264    
181.mcf base result bar (318)
181.mcf peak result bar (318)
181.mcf 16 105    318     16 105    318    
186.crafty base result bar (222)
186.crafty peak result bar (222)
186.crafty 16 83.7  222     16 83.7  222    
197.parser base result bar (177)
197.parser peak result bar (177)
197.parser 16 189    177     16 189    177    
252.eon base result bar (287)
252.eon peak result bar (287)
252.eon 16 84.2  287     16 84.2  287    
253.perlbmk base result bar (218)
253.perlbmk peak result bar (218)
253.perlbmk 16 153    218     16 153    218    
254.gap base result bar (160)
254.gap peak result bar (160)
254.gap 16 128    160     16 128    160    
255.vortex base result bar (342)
255.vortex peak result bar (342)
255.vortex 16 103    342     16 103    342    
256.bzip2 base result bar (222)
256.bzip2 peak result bar (222)
256.bzip2 16 125    222     16 125    222    
300.twolf base result bar (238)
300.twolf peak result bar (238)
300.twolf 16 234    238     16 234    238    
  SPECint_rate_base2000 229      
  SPECint_rate2000 229    

Hardware
Hardware Vendor: Hewlett-Packard Company
Model Name: HP Integrity Superdome 16-way (1500 MHz Itanium 2)
CPU: Intel Itanium 2
CPU MHz: 1500
FPU: Integrated
CPU(s) enabled: 16 cores, 16 chips, 1 core/chip
CPU(s) orderable: 6 to 16 by 2
Parallel: no
Primary Cache: 16KBI + 16KBD (on chip) per CPU
Secondary Cache: 256KB (on chip) per CPU
L3 Cache: 6.0MB (on chip) per CPU
Other Cache: N/A
Memory: 64GB (128 * 512MB DIMMs)
Disk Subsystem: 10x36GB 10K RPM SCSI disk (striped)
Other Hardware: N/A
Software
Operating System: HPUX11i-TCOE B.11.23
Compiler: HP C/ANSI C Compiler B.11.23
HP aC++ Compiler B.11.23
File System: hfs
System State: Multi-user
Notes / Tuning Information
 Portability Flags
 176.gcc     : -DHOST_WORDS_BIG_ENDIAN
 186.crafty  : -DHP
 252.eon     : -DFMAX_IS_DOUBLE 
 253.perlbmk : -DSPEC_CPU2000_HP
 254.gap     : -DSPEC_CPU2000_HP -DSYS_IS_USG -DSYS_HAS_IOCTL_PROTO
               -DSYS_HAS_TIME_PROTO -DSYS_HAS_CALLOC_PROTO
 
 Base Flags
   all       : +Oprofile=collect:all/+Oprofile=use
   C         : +Ofaster -exec +Odatalayout
   C++       : +Ofaster +inline_level 2 -minshared 
 
 Peak Flags
   same as baseline (basepeak=true set globally)

 Kernel Tunables:
   dbc_max_pct=20
   dbc_min_pct=20
   maxdsiz=3221225472
   maxssiz=401604608
   maxdsiz_64bit=4396972769279
   maxssiz_64bit=1073741824
   vps_pagesize=4096
   vps_ceiling=16384

 Notes:

   System was configured with 1/2 of memory interleaved and
     1/2 of memory local to each cell

   System configured as a single partition with 4 cells and 
     4 processors per cell

   Processes were assigned to localities using the
     HP-UX mpsched utility

   Filesystem used for spec runs mounted fs_async
 


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Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 07-Oct-2003

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