SPEC Seal of Reviewal CINT2000 Result
Copyright © 1999-2004 Standard Performance Evaluation Corporation
IBM Corporation
IBM eServer p5 510 (1650 MHz, 2 CPU)
SPECint_rate2000 = 33.0  
SPECint_rate_base2000 = 31.6  
SPEC license # 11 Tested by: IBM Test date: Jan-2005 Hardware Avail: Feb-2005 Software Avail: Dec-2004
Graph Scale Benchmark Base
Copies		 Base
Runtime		 Base
Ratio		 Copies Runtime Ratio
164.gzip base result bar (23.9)
164.gzip peak result bar (24.2)		 164.gzip 4 272    23.9   4 268    24.2  
175.vpr base result bar (26.8)
175.vpr peak result bar (27.1)		 175.vpr 4 242    26.8   4 240    27.1  
176.gcc base result bar (36.6)
176.gcc peak result bar (36.7)		 176.gcc 4 139    36.6   4 139    36.7  
181.mcf base result bar (40.3)
181.mcf peak result bar (41.7)		 181.mcf 4 207    40.3   4 200    41.7  
186.crafty base result bar (25.4)
186.crafty peak result bar (33.8)		 186.crafty 4 183    25.4   4 137    33.8  
197.parser base result bar (31.3)
197.parser peak result bar (31.3)		 197.parser 4 267    31.3   4 267    31.3  
252.eon base result bar (38.9)
252.eon peak result bar (40.0)		 252.eon 4 155    38.9   4 151    40.0  
253.perlbmk base result bar (24.5)
253.perlbmk peak result bar (26.4)		 253.perlbmk 4 341    24.5   4 317    26.4  
254.gap base result bar (26.8)
254.gap peak result bar (26.8)		 254.gap 4 191    26.8   4 191    26.8  
255.vortex base result bar (46.9)
255.vortex peak result bar (51.0)		 255.vortex 4 188    46.9   4 173    51.0  
256.bzip2 base result bar (34.9)
256.bzip2 peak result bar (34.8)		 256.bzip2 4 200    34.9   4 200    34.8  
300.twolf base result bar (31.8)
300.twolf peak result bar (31.8)		 300.twolf 4 438    31.8   4 438    31.8  
  SPECint_rate_base2000 31.6    
  SPECint_rate2000 33.0  

Hardware
Hardware Vendor: IBM Corporation
Model Name: IBM eServer p5 510 (1650 MHz, 2 CPU)
CPU: POWER5
CPU MHz: 1650
FPU: Integrated
CPU(s) enabled: 2 cores, 1 chip, 2 cores/chip (SMT on)
CPU(s) orderable: 1,2
Parallel: no
Primary Cache: 64KBI+32KBD (on chip)/core
Secondary Cache: 1920KB unified (on chip)/chip
L3 Cache: 36MB unified (off-chip)/DCM, 1 DCM/SUT
Other Cache: None
Memory: 8x4GB
Disk Subsystem: 2x36GB SCSI, 15K RPM
Other Hardware: None
Software
Operating System: AIX 5L V5.3
Compiler: XL C/C++ Enterprise Edition Version 7.0 for AIX
File System: AIX/JFS2
System State: Multi-user
Notes / Tuning Information 
 Portability Flags:
   176.gcc:      -ma -DHOST_WORDS_BIG_ENDIAN
   186.crafty:   -DAIX
   252.eon:      srcalt=fmax_errno
                 -I.
   253.perlbmk:  -DSPEC_CPU2000_AIX
   254.gap:      -DSYS_IS_BSD -DSYS_STRING_H -DSYS_HAS_TIME_PROTO
                 -DSYS_HAS_MALLOC_PROTO -DSYS_HAS_CALLOC_PROTO
   300.twolf:    -DHAVE_SIGNED_CHAR

 Base Optimization Flags:
   C:    -qpdf1/pdf2
         -O5 -blpdata -D_ILS_MACROS
   C++:  -qpdf1/pdf2
         -O5 -lhmu -qalign=natural

 Peak Optimization Flags
   164.gzip:     -qpdf1/pdf2
                 fdpr -q -O3
                 -O5 -blpdata -qfdpr
   175.vpr:      -qpdf1/pdf2
                 -O5 -blpdata -qalign=natural -D_ILS_MACROS
   176.gcc:      -qpdf1/pdf2
                 -O5 -blpdata -D_ILS_MACROS
   181.mcf:      fdpr -q -O3
                 -O5 -blpdata -qfdpr
   186.crafty:   -qpdf1/pdf2
                 fdpr -q -O3
                 -O4 -q64 -qfdpr -qarch=pwr3 -qtune=pwr3
   197.parser:   -qpdf1/pdf2
                 -O5 -blpdata -qalign=natural -D_ILS_MACROS
   252.eon:      -qpdf1/pdf2
                 -O4 -qarch=auto -qtune=auto -qalign=natural -D_ILS_MACROS
   253.perlbmk:  -qpdf1/pdf2
                 -O5 -lhmu -qalign=natural -blpdata -D_ILS_MACROS
   254.gap:      basepeak=1
   255.vortex:   -qpdf1/pdf2
                 -O5 -lhmu -qalign=natural -blpdata
   256.bzip2:    fdpr -q -O3
                 -O5 -blpdata -qfdpr -D_ILS_MACROS
   300.twolf:    basepeak=1

 Approved alternate-source file 252.eon.fmax_errno.src.alt.tar.gz
 was used with 252.eon for POSIX-compatibility.

 APAR IY62267 was applied to AIX 5L V5.3 to achieve Mantainence Level 1.

 SMT:  Acronym for "Simultaneous Multi-Threading". A processor technology that allows
       the simultaneous execution of multiple thread contexts within a single processor
       core. (Enabled by default)
 DCM:  Acronym for "Dual-Chip Module" (one dual-core processor chip + one L3-cache chip)
 SUT:  Acronym for "System Under Test"

 ulimits set to unlimited.
 Large page mode, memory affinity, and shared-memory pinning were set as follows:
     vmo -r -o lgpg_regions=200 -o lgpg_size=16777216 -o memory_affinity=1 -o v_pinshm=1
     chuser capabilities=CAP_BYPASS_RAC_VMM,CAP_PROPAGATE $USER
     reboot -q
     export MEMORY_AFFINITY=MCM

 The following config-file entry was used to assign each benchmark process to a core:
      submit = let "MYCPU=2*\$SPECUSERNUM"; if (("\$MYCPU > 15")) then let "MYCPU-=15"; fi; bindprocessor \$\$ \$MYCPU; $command
 The "bindprocessor" AIX command binds a process to a CPU core.

For questions about this result, please contact the tester.
For other inquiries, please contact webmaster@spec.org
Copyright © 1999-2004 Standard Performance Evaluation Corporation

First published at SPEC.org on 22-Feb-2005

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