Intergraph Corporation
TDZ300 (180MHz)


SPECint95 7.22
SPECint_base95 7.22

Benchmark # and Name Reference Time Base Run Time Base SPEC Ratio Peak Run Time Peak SPEC Ratio
099.go 46006287.336287.33
124.m88ksim 19002707.032707.03
126.gcc 17002486.862486.86
129.compress 18003045.933045.93
130.li 19002487.662487.66
132.ijpeg 24003177.573177.57
134.perl 19002567.412567.41
147.vortex 27003318.153318.15
SPECint_base95 7.22
SPECint95 7.22

Tester Information:
SPEC License #: 14
Tested By: Intel
Test Date: Oct-95
Hardware Avail: Mar-96
Software Avail: Feb-96

Hardware Information:
Model Name: TDZ300
CPU: 180MHz Pentium Pro Processor
FPU: Integrated
Number of CPU(s): 1
Primary Cache: 8KBI+8KBD
Secondary Cache: 256KB(I+D)
Other Cache: None
Memory: 128MB (60ns fast page)
Disk Subsystem: 2GB ST32550W
Other Hardware: AHA-2940W Controller

Software Information:
Operating System: UnixWare 2.0, SDK
Compiler: Intel C Reference Compiler 2.2 Beta
File System: ufs, vxfs (/tmp as 8MB /tmpfs)
System State: Single user (root + killall)

Notes:
Base and non-base flags are the same and use Feedback Directed Optimization
Pass1: -tp p6 -ipo -xi -prof_gen -ircdb_dir /tmp/IRCDB
Pass2: -tp p6 -ipo -xi -prof_use -ircdb_dir /tmp/IRCDB
-ircdb_dir is a location flag and not an optimization flag
Portability: 124: -DSYSV -DLEHOST 130, 134, 147: -lm  132: -DSYSV  126: -lm -lc -L/usr/ucblib -lucb -lmalloc
Memory subsystem is four-way interleaved.  Fastest memory timings selected in bios.
200MHz processor clocked to 180MHz (change in oscillator) for test purposes

If you wish to print this information we highly recommend using the postscript reporting page.

This page was generated with runspec 95.55.

For more information contact:
SPEC
10754 Ambassador Drive, Suite 201 Manassas, VA, 22110